// Copyright (C) 1953-2022 NUDT
// Verilog module name - flow_sort
// Version: V4.0.0.20220524
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         lookup dmac forward table.
///////////////////////////////////////////////////////////////////////////


module flow_sort
(
        i_clk     , 
        i_rst_n   ,
        
        iv_broadcast_storm_prevent_outport,
                  
        iv_md     ,
        i_md_wr   ,
        
        ov_md     ,
		o_md_wr   
);
// I/O
// clk & rst  
input               i_clk  ;
input               i_rst_n;

input       [32:0]  iv_broadcast_storm_prevent_outport;
//
input       [299:0] iv_md  ;
input               i_md_wr;

output reg  [299:0] ov_md;
output reg          o_md_wr;
//***************************************************
//          lookup dmac forward table
//***************************************************
// internal reg&wire for state machine 

always @(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n)begin
        ov_md   <= 300'b0;
        o_md_wr <= 1'b0;
    end
    else begin
        if(i_md_wr)begin
            if(iv_md[47:0] == 48'hff_ff_ff_ff_ff_ff)begin//broadcast
                ov_md[299:199] <= iv_md[299:199];
                ov_md[199] <= iv_md[199];
                ov_md[198:166] <= (~{33'd1 << iv_md[198:166]}) & iv_broadcast_storm_prevent_outport;//outport
                ov_md[165:0]   <= iv_md[165:0];
                o_md_wr        <= 1'b1;              
            end
            else begin
                ov_md   <= iv_md;
                o_md_wr <= 1'b1;              
            end                
        end
        else begin
            ov_md   <= 300'b0;
            o_md_wr <= 1'b0;        
        end
    end
end
endmodule           